Company:Qualcomm Technologies International Ltd

Job Area:Engineering Group, Engineering Group > ASICS Engineering

General Summary:

We are searching for a Staff level radio frequency integrated circuit (RFIC)/Analogue layout engineer to join a strong group of RFIC designers to help lead Qualcomm in the development of RF transceivers to address the IoT market. Working within a dynamic design team you will participate in the development of next generation RFIC products in the IoT wireless space. 

RESPONSIBILITIES:

Lead the physical layout of complex RFICs.Define and enforce layout methodologies, best practices, and quality standards across the layout team.Collaborate with RFIC design, packaging, and verification teams to ensure optimal performance and manufacturability.Drive technical reviews, mentor junior and senior layout engineers, and provide layout planning support to project lead.Own the full layout lifecycle from floorplanning to tape-out, including DRC/LVS/PEX sign-off and post-layout optimization.

PROFILE:

Highly motivated, pro-active self-starterStrong sense of ownership and responsibilityCreative thinker with strong problem-solving skillsTeam oriented attitudeAbility to thrive in a multicultural environmentAbility to communicate well with cross-functional teamsExcellent written and oral communications skills

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

REQUIRED EXPERIENCE:

10+ years of hands-on RFIC layout experience in advanced CMOS and/or BiCMOS technologies.Full appreciation of RF and analogue layout techniques in low geometry nodes (22nm or lower)Proven leadership in delivering multiple successful RFIC tape-outs, including high-frequency and mixed-signal designs.Experience leading layout teams or acting as a technical authority in layout methodology and execution across multiple geographical locations.Fluent English speaker

REQUIRED DETAILED KNOWLEDGE:

Expert-level proficiency in Cadence Virtuoso and advanced layout techniques for RF blocks (LNAs, mixers, VCOs, PAs, PLLs).Deep understanding of parasitic-aware layout, matching, shielding, isolation, and substrate noise mitigation.Strong command of DRC, LVS, and PEX flows, including debugging and optimization.Familiarity with ESD, latch-up prevention, and reliability-aware layout practices.Experience with layout planning for high-density, high-performance RFICs.

PREFERRED DETAILED KNOWLEDGE:

Scripting and automation using SKILL, Python, or TCL to enhance layout productivity.Familiarity with advanced process nodes (e.g., 16nm, 7nm) and 3DIC/heterogeneous integration.Knowledge of EM simulation tools (e.g., HFSS, Momentum) and their integration into layout flows.

ADDITIONAL USEFUL EXPERIENCE:

Exposure to RFIC design principles and ability to interpret schematics and simulation results.Contributions to EDA tool evaluation, layout methodology development, or academic publications.Cross-site collaboration and experience working in global teams.

KEY WORDS:

CMOSIoTRF and analogue layoutCadence+10 years’ experience in RFIC design

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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