**Summary:** Facebook is hiring ASIC Design Engineers within our Infrastructure organization. We are looking for talented individuals with deep experience that span one or more of the key areas required to build successful world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer Design Responsibilities: 1. Architecture exploration 2. Micro-architecture development 3. RTL development using Verilog, System Verilog and HLS 4. Lint, CDC, Synthesis, & Power Optimization 5. Soft and hard IP identification, selection and integration 6. Collaboration with verification and emulation teams in test plan development and debug 7. Collaboration with implementation team to close the design on timing and power **Minimum Qualifications:** Minimum Qualifications: 8. At least 7+ years of silicon development experience 9. Track record of first-pass success in ASIC Development 10. Experience with Verilog or System Verilog 11. Experience in one of these skills: Micro-architecture and RTL development for complex control and data path IPs, OR Experience in SoC Micro-architecture, Design and Integration, OR Implementation, Power methodology development 12. Experience working across multiple projects 13. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. **Preferred Qualifications:** Preferred Qualifications: 14. Experience in data path development 15. Experience in CPU, NOC, Memory and Peripheral Subsystems 16. Experience in HLS 17. Experience with Synthesis, Timing Closure and Formal Verification Methodology 18. Experience with Power Analysis and Optimization 19. Experience with scripting languages (TCL, Python, Perl, Shell-scripting) **Industry:** Internet